Arts & Sciences Events
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Arts & Sciences
[PAST EVENT] Emerging Nonvolatile Memory Technology based Future Main Memory System
March 4, 2016
8am - 9am
Title: "Emerging Nonvolatile Memory Technology based Future Main Memory System"
Lei Jiang, AMD
Abstract:
Main memory scaling is in great peril as cell size remains constant and power consumption rises at the latest technology generation for traditional memory technologies, such as dynamic random access memory (DRAM). Recent innovations have identified emerging nonvolatile memories, such as phase change memory (PCM), as scalable solutions to boost memory capacity in a power efficient manner. Multi-level cell (MLC) PCM storing multiple bits in a single cell further increases storage density with a lower cost per bit. However, to deploy MLC PCM as a DRAM alternative and to exploit its scalability, MLC PCM must be architected to overcome its own disadvantages such as long write latency, short cell endurance and large write power. In this talk, I will present several architectural techniques to overcome these shortcomings for MLC PCM based memory systems.
Bio:
Lei Jiang received his B.S. and M.S. from Shanghai Jiao Tong University China in 2006 and 2009, respectively. Lei completed his Ph.D. in the University of Pittsburgh, Dec. 2014. He is working at AMD. His research topic includes phase change memory, STT-MRAM and Memristor. He is the co-recipient of the best paper award of the International Symposium on Low Power Electronics and Design (ISLPED) in 2013.
Lei Jiang, AMD
Abstract:
Main memory scaling is in great peril as cell size remains constant and power consumption rises at the latest technology generation for traditional memory technologies, such as dynamic random access memory (DRAM). Recent innovations have identified emerging nonvolatile memories, such as phase change memory (PCM), as scalable solutions to boost memory capacity in a power efficient manner. Multi-level cell (MLC) PCM storing multiple bits in a single cell further increases storage density with a lower cost per bit. However, to deploy MLC PCM as a DRAM alternative and to exploit its scalability, MLC PCM must be architected to overcome its own disadvantages such as long write latency, short cell endurance and large write power. In this talk, I will present several architectural techniques to overcome these shortcomings for MLC PCM based memory systems.
Bio:
Lei Jiang received his B.S. and M.S. from Shanghai Jiao Tong University China in 2006 and 2009, respectively. Lei completed his Ph.D. in the University of Pittsburgh, Dec. 2014. He is working at AMD. His research topic includes phase change memory, STT-MRAM and Memristor. He is the co-recipient of the best paper award of the International Symposium on Low Power Electronics and Design (ISLPED) in 2013.