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[PAST EVENT] Computer Science Colloquium: MemAxes: A tool for dissecting on-node memory performance data
October 17, 2014
1pm
Todd Gambiln, Lawrence Livermore National Laboratory
Memory optimization has long been a major performance bottleneck, and this trend continues as node architectures with complex non-uniform memory access (NUMA) hierarchies become the norm. The performance monitoring units (PMU) on recent processors can provide extremely detailed memory performance information, but it is difficult to meaningfully interpret this data using manual analysis.
We have developed MemAxes, a tool that maps metadata from sampled memory instructions onto views of the node architecture, application data structures, source code, and parallel coordinates. Our tool provides the context necessary to interpret the data and to gain insight into memory-related performance problems. In this presentation we describe our measurement techniques and the mapping techniques used to effectively display performance data in MemAxes.
Bio:
Dr. Gamblin is a computer scientist in the Center for Applied Scientific Computing at Lawrence Livermore National Laboratory. His research focuses on scalable tools for measuring, analyzing, and visualizing performance data from massively parallel applications. He is also involved with many production projects at LLNL. He works with Livermore Computing's Development Environment Group to build tools that allow users to deploy, run, debug, and optimize their software for machines with million-way concurrency.
Dr. Gamblin received his Ph.D. in computer science from the University of North Carolina at Chapel Hill in 2009. His dissertation investigated parallel methods for compressing and sampling performance measurements from hundreds of thousands of concurrent processors. He received his B.A. in Computer Science and Japanese from Williams College in 2002. He has also worked as a software developer in Tokyo and held research internships at the University of Tokyo and IBM Research.
Memory optimization has long been a major performance bottleneck, and this trend continues as node architectures with complex non-uniform memory access (NUMA) hierarchies become the norm. The performance monitoring units (PMU) on recent processors can provide extremely detailed memory performance information, but it is difficult to meaningfully interpret this data using manual analysis.
We have developed MemAxes, a tool that maps metadata from sampled memory instructions onto views of the node architecture, application data structures, source code, and parallel coordinates. Our tool provides the context necessary to interpret the data and to gain insight into memory-related performance problems. In this presentation we describe our measurement techniques and the mapping techniques used to effectively display performance data in MemAxes.
Bio:
Dr. Gamblin is a computer scientist in the Center for Applied Scientific Computing at Lawrence Livermore National Laboratory. His research focuses on scalable tools for measuring, analyzing, and visualizing performance data from massively parallel applications. He is also involved with many production projects at LLNL. He works with Livermore Computing's Development Environment Group to build tools that allow users to deploy, run, debug, and optimize their software for machines with million-way concurrency.
Dr. Gamblin received his Ph.D. in computer science from the University of North Carolina at Chapel Hill in 2009. His dissertation investigated parallel methods for compressing and sampling performance measurements from hundreds of thousands of concurrent processors. He received his B.A. in Computer Science and Japanese from Williams College in 2002. He has also worked as a software developer in Tokyo and held research internships at the University of Tokyo and IBM Research.