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Abstract:

Graphics processing units (GPUs) have been increasingly used to accelerate a variety of

data-parallel applications. By exploiting massive thread-level parallelism (TLP), GPUs

can achieve high throughput as well as memory latency hiding. As a result, a very large

register file (RF) is typically required to enable fast and low-cost context switching

between tens of thousands of active threads. In this talk, I will introduce our recent

research on GPU register file management to enhance GPU performance and energy

efficiency. Since a large percentage of data in GPGPU applications actually have fewer

significant bits compared to the full width of a 32-bit register, the narrow-width operands

can be packed together to improve register utilization and increase the occupancy of GPU

threads. Several leakage management techniques for GPU register files will also be

introduced to reduce the leakage and total energy dissipation.

Bio:

Dr. Wei Zhang is a professor in the Department of Electrical and Computer Engineering

at Virginia Commonwealth University (VCU). He received his Ph.D. from the

Pennsylvania State University in 2003. From August 2003 to July 2010, Dr. Zhang

worked as an assistant professor and then as a tenured associate professor at Southern

Illinois University Carbondale (SIUC). His research interests are in embedded and real-

time computing systems, computer architecture, and compiler. Dr. Zhang is the director

of Nvidia CUDA Research Center at VCU. He received the 2016 Engineer of the Year

Award from Richmond Joint Engineer Council, the 2009 SIUC Excellence through

Commitment Outstanding Scholar Award for the College of Engineering, and 2007 IBM

Real-time Innovation Award. He has been the PI for seven NSF projects as well as

projects funded by industry such as IBM, Intel, and Nvidia.

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